Silicon & IP

The RapidIO® Interconnect Architecture is an industry-standard, high-performance, packet-based interconnect technology that provides a high-speed interconnect between network processing units (NPUs), central processing units (CPUs), and digital signal processors (DSPs). It addresses the need for a standards-based, high-speed, reliable interconnect and is targeted at the networking, embedded, and storage markets. RapidIO allows chip-to-chip, board-to-board, and system-to-system communications scaling to 10 Gbps and beyond.

Mercury Computer Systems' RapidIO IP core is designed for the growing RapidIO market. The core is a high-performance solution that is independent of physical layer designs, implementation tools, and target technology. It is capable of addressing a variety of solutions, including endpoint and switching applications.

The Mercury RapidIO IP is available for both application-specific integrated circuits (ASICs) and field-programmable gate arrays (FPGAs). It is designed for reuse and is optimized for performance, latency, and reliability. It is capable of addressing a variety of solutions, including endpoint and switching applications. It has a well-defined host interface to ease integration into a variety of host interface designs.

Products

MC432 Serial RapidIO 8-Port Switch IC
The MC432 serial RapidIO 8-port switch IC has 8 ports of 4x lanes, allowing developers to take advantage of the benefits of serial RapidIO technology for embedded, communications, networking, and storage applications. The switch provides 64 Gb/s of bandwidth, and each port has four full-duplex serial transceivers.The switch incorporates SerDes functionality with 8/10-bit encoding. It also includes standard RapidIO features such as error recovery, priority-based routing, deadlock prevention mechanisms, and full multicast support, which allows a single endpoint to send the same data block to more than one receiver using port masks. It has input buffering for up to 28 full-size RapidIO packets.

Serial FPDP IP Core
The Serial FPDP IP Core is designed for serial front-panel data port (SFPDP) applications. The core is a high-performance solution that is independent of physical layer designs, implementation tools, and target technology. It is capable of addressing a variety of solutions, including sensor to processor and storage applications. The VITA SFPDP Interconnect technology is an industry-standard, high-performance, front panel interconnect technology that provides a high-speed interconnect between sensors, processors and storage devices. It addresses the need for a standards-based, high-speed, reliable interconnect and is targeted at the sensor and storage markets. Chip-to-chip, board-to-board, and system-to-system communications scaling to 10 Gbps and beyond. Serial FPDP is protocol-agnostic, supporting several existing interconnect standards including serial RapidIO© and PCI Express©.

Serial RapidIO IP Core
Serial RapidIO IP Core is a high-performance solution that is independent of physical layer designs, implementation tools, and target technology. It is capable of addressing a variety of solutions, including endpoint and switching applications. The core is designed for the growing RapidIO market.The RapidIO Interconnect Architecture is an industry-standard, high-performance, packet-based interconnect technology that provides a high-speed interconnect between NPUs, CPUs, and DSPs. It addresses the need for a standards-based, high-speed, reliable interconnect and is targeted at the networking, embedded, and storage markets. Serial RapidIO allows chip-to-chip, board-to-board, and system-to-system communications scaling to 10 Gbps and beyond.

Serial RapidIO-to-PCIe Intelligent Bridge IP Core
The Serial RapidIO-to-PCIe Intelligent Bridge IP Core is architected for applications requiring high-bandwidth bridging between PCI Express® (PCIe) devices and serial RapidIO® digital signal processors (DSPs), processors, and switch fabric. The IP connects a serial RapidIO port operating up to 3.125 GHz to an 8x PCI Express port operating at 2.5 GHz through an intelligent non-transparent bridge. Sophisticated queuing within the intelligent bridge assures the highest utilization of available port bandwidth.The Serial RapidIO-to-PCIe Intelligent Bridge IP Core is designed for bridging the growing number of RapidIO and PCI Express applications. The core is independent of physical layer designs, implementation tools, and target technology, and is capable of addressing a variety of solutions for ASICs and FPGAs.

Whitepapers

RapidIO Technology Solves the Communication Fabric Conundrum
While business conditions are influencing equipment vendors to consider adopting an open standard, multiple technologies are vying to be the fabric of choice for networking and communications. The RapidIO standard is the only one that is mature, scales and specifically addresses the full requirements of the communication fabric space. This article covers features included to meet these requirements. This article is reproduced with the courtesy of the Rapid IO Trade Association.

Tutorials

Rapid IO Technology Overview and Applications
This tutorial addresses the Rapid IO concept of peer to peer communication and also the transactions occurring in the Logical, Transport and Physical layers of the Serial Rapid IO protocol. It has an abundance of applications where this Standard Based Interconnect is being deployed for numerous designs. This article is reproduced with the courtesy of the Rapid IO Trade Association

Mercury's Serial RapidIO IP Core Technical Presentation
As customers need to implement systems and need proof of concept expeditiously they need to have robust IP available that is also FPGA-agnostic. This detailed presentation describes the full feature set available with the Mercury Serial RapidIO IP Core.

A SIGINT Acquisition Demonstration Using RapidIO
The RapidIO architecture is ideal for high-performance, low latency computing. This presentation reviews the implementation of a radio frequency (RF) channelizing system that detects the time and frequency of each hop transmission from a frequency-hopping emitter.